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DATA SHEET
MOS INTEGRATED CIRCUIT
PD753012A, 753016A, 753017A
4-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD753017A is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional PD75316B, and can provide high-speed operation at a low supply voltage of 1.8 V. It can be supplied in a small plastic TQFP package (12 x 12 mm) and is suitable for small sets using LCD panels. Detailed descriptions of functions are provided in the following document. Be sure to read the document before designing.
PD753017 User's Manual : U11282E
FEATURES
* Low voltage operation: VDD = 1.8 to 5.5 V * Can be driven by two 1.5 V batteries * On-chip memory * Program memory (ROM): 12288 x 8 bits (PD753012A) 16384 x 8 bits (PD753016A) 24576 x 8 bits (PD753017A) * Data memory (RAM): 1024 x 4 bits * Capable of high-speed operation and variable instruction execution time for power saving * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation) * 122 s (at 32.768 kHz operation) * Internal programmable LCD controller/driver * Small plastic TQFP (12 x 12 mm) * Suitable for small sets such as cameras * One-time PROM: PD75P3018A
APPLICATION
Remote controllers, camera-integrated VCRs, cameras, gas meters, etc.
In this document, unless otherwise specified, the description is made based on PD753017A as typical product.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11662EJ2V0DS00 (2nd edition) Date Published July 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1996, 2000
PD753012A, 753016A, 753017A
ORDERING INFORMATION
Part number Package 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm)
PD753012AGC-XXX-3B9 PD753012AGC-XXX-8BT PD753012AGK-XXX-BE9 PD753012AGK-XXX-9EU PD753016AGC-XXX-3B9 PD753016AGC-XXX-8BT PD753016AGK-XXX-BE9 PD753016AGK-XXX-9EU PD753017AGC-XXX-3B9 PD753017AGC-XXX-8BT PD753017AGK-XXX-BE9 PD753017AGK-XXX-9EU
Remark
XXX indicates ROM code suffix.
2
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
FUNCTION OUTLINE
Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: at 6.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) ROM 12288 x 8 bits (PD753012A) 16384 x 8 bits (PD753016A) 24576 x 8 bits (PD753017A) RAM General purpose register 1024 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 16 8 8 On-chip pull-up resistors can be specified by using software: 23 Also used for segment pins Withstands 13 V, on-chip pull-up resistors can be specified by using mask option
Internal memory
Input/ output port
CMOS input CMOS input/output CMOS output N-ch open-drain input/output Total
40 * Segment number selection * Display mode selection : 24/28/32 segments (can be changed to CMOS output port in 4 time-unit; max. 8) : Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias)
LCD controller/driver
On-chip split resistor for LCD drive can be specified by using mask option Timer 5 channels * 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) * Basic interval timer/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 16 bits * , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) External: 3, Internal: 5 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Serial interface
Bit sequential buffer Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt Test input System clock oscillator
Standby function Power supply voltage Package
Data Sheet U11662EJ2V0DS00
3
PD753012A, 753016A, 753017A
CONTENTS
1. PIN CONFIGURATION (Top View) ..................................................................................................... 6 2. BLOCK DIAGRAM ............................................................................................................................... 8 3. PIN 3.1 3.2 3.3 3.4 FUNCTION .................................................................................................................................... 9 Port Pins ...................................................................................................................................... 9 Non-port Pins ............................................................................................................................ 11 Pin Input/Output Circuits ......................................................................................................... 13 Recommended Connection for Unused Pins ......................................................................... 15
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ......................................... 16 4.1 Differences between Mk I Mode and Mk II Mode .................................................................... 16 4.2 Setting Method of Stack Bank Select Register (SBS) ........................................................... 17 5. MEMORY CONFIGURATION ............................................................................................................18 6. PERIPHERAL HARDWARE FUNCTIONS ....................................................................................... 23 6.1 Digital Input/Output Ports ........................................................................................................ 23 6.2 Clock Generator ........................................................................................................................24 6.3 Subsystem Clock Oscillator Control Functions .................................................................... 25 6.4 Clock Output Circuit .................................................................................................................26 6.5 Basic Interval Timer/Watchdog Timer ..................................................................................... 27 6.6 Watch Timer ..............................................................................................................................28 6.7 Timer/Event Counter .................................................................................................................29 6.8 Serial Interface .......................................................................................................................... 33 6.9 LCD Controller/Driver ............................................................................................................... 35 6.10 Bit Sequential Buffer ................................................................................................................ 37 7. INTERRUPT FUNCTION AND TEST FUNCTION .......................................................................... 38 8. STANDBY FUNCTION .......................................................................................................................40 9. RESET FUNCTION ............................................................................................................................ 41 10. MASK OPTION .................................................................................................................................. 44 11. INSTRUCTION SET ........................................................................................................................... 45 12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 57 13. CHARACTERISTICS CURVES (REFERENCE VALUES) .............................................................. 71 14. PACKAGE DRAWINGS ..................................................................................................................... 73 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 77
4
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST ........................................... 79 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 81 APPENDIX C. RELATED DOCUMENTS ................................................................................................ 85
Data Sheet U11662EJ2V0DS00
5
PD753012A, 753016A, 753017A
1. PIN CONFIGURATION (Top View)
* 80-pin plastic QFP (14 x 14 mm)
PD753012AGC-XXX-3B9, 753012AGC-XXX-8BT, 753016AGC-XXX-3B9, 753016AGC-XXX-8BT PD753017AGC-XXX-3B9, 753017AGC-XXX-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD753012AGK-XXX-BE9, 753012AGK-XXX-9EU, 753016AGK-XXX-BE9, 753016AGK-XXX-9EU PD753017AGK-XXX-BE9, 753017AGK-XXX-9EU
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1
S11 S10 S9 S8
P60/KR0 X2 X1 ICNote XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2/TI1/TI2 P11/INT1 P10/INT0 P03/SI/SB1
Note Connect the IC (Internally Connected) pin directly to VDD.
6
COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
Data Sheet U11662EJ2V0DS00
COM0 COM1 COM2
PD753012A, 753016A, 753017A
Pin Identification BIAS BP0-BP7 BUZ COM0-COM3 IC INT2 KR0-KR7 LCDCL P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 : LCD Power Supply Bias Control : Bit Port : Buzzer Clock : Common Output 0-3 : Internally Connected : External Test Input 2 : Key Return : LCD Clock : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 PCL RESET S0-S31 SB0, SB1 SCK SI SO SYNC TI0-TI2 VDD VLC0-VLC2 VSS X1, X2 XT1, XT2 : Programmable Clock : Reset Input : Segment Output 0-31 : Serial Bus 0, 1 : Serial Clock : Serial Input : Serial Output : LCD Synchronization : Timer Input 0-2 : Positive Power Supply : LCD Power Supply 0-2 : Ground : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 PTO0-PTO2 : Programmable Timer Output 0-2
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
Data Sheet U11662EJ2V0DS00
7
PTO1/P21
TI1/TI2/ P12/INT2
8
INTT1 BASIC INTERVAL /WATCHDOG TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TOUT0 BUZ/P23 WATCH TIMER
Data Sheet U11662EJ2V0DS00
2. BLOCK DIAGRAM
PTO2/P22/PCL TOUT0 INTT2
TIMER/EVENT COUNTER #1
TIMER/EVENT COUNTER #2
PORT0 PORT1 SP (8) ALU CY SBS BANK PORT2
4 4 4 4 4 4 4 4
P00-P03 P10-P13 P20-P23
PROGRAM COUNTERNote 1
PORT3 PORT4 PORT5 PORT6 PORT7
P30-P33 P40-P43 P50-P53 P60-P63 P70-P73
GENERAL REG. INTW SI/SB1/P03 SO/SB0/P02 SCK/P01 INTCSI TOUT0 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60- 8 KR7/P73 BIT SEQ. BUFFER (16) fx/2N CLOCK OUTPUT CONTROL CLOCK DIVIDER INTERRUPT CONTROL CPU CLOCK
SYSTEM CLOCK GENERATOR
fLCD
CLOCKED SERIAL INTERFACE
ROMNote 2 PROGRAM MEMORY
DECODE AND CONTROL
RAM DATA MEMORY 1024 X 4 BITS
PD753012A, 753016A, 753017A
24 8 LCD CONTROLLER /DRIVER 4 3 fLCD
S0-S23 S24/BP0S31/BP7 COM0-COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
SUB
MAIN
STAND BY CONTROL
PCL/PTO2/P22
XT1 XT2 X1 X2
IC
VDD
VSS RESET
Notes 1. 2.
PD753012A and 753016A have a 14-bit configuration, and PD753017A has a 15-bit configuration.
Capacity of the ROM depends on the product.
PD753012A, 753016A, 753017A
3. PIN FUNCTION 3.1 Port Pins (1/2)
Alternate Function INT4 SCK SO/SB0 SI/SB1 Input INT0 INT1 TI1/TI2/INT2 TI0 I/O PTO0 PTO1 PCL/PTO2 BUZ I/O LCDCL SYNC - - I/O - Programmable 4-bit input/output port (PORT3). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistor can be specified by software in 4-bit units. N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. No Input E-B 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. Only P10/INT0 can select noise elimination circuit. 4-bit input/output port (PORT2). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No input 8-bit I/O Circuit After Reset I/O Type Note 1 No Input -A -B -C -C
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40-P43 Note 2
I/O Input
Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pullup resistors can be specified by software in 3-bit units.
No
Input
E-B
Yes
High level (when pullup resistors are provided) or high impedance High level (when pullup resistors are provided) or high impedance
M-D
P50-P53 Note 2
I/O
-
M-D
Notes 1. 2.
Circuit types enclosed in brackets indicate the Schmitt trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed.
Data Sheet U11662EJ2V0DS00
9
PD753012A, 753016A, 753017A
3.1 Port Pins (2/2)
Alternate Function KR0 KR1 KR2 KR3 I/O KR4 KR5 KR6 KR7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 1-bit output port (BIT PORT). Also used for segment output pins. No Note 2 H-A 8-bit I/O Circuit After Reset I/O TypeNote 1 Yes Input -A
Pin Name P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7
I/O I/O
Function Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. 4-bit input/output port (PORT7). Connection of on-chip pull-up resistors can be specified by software in 4-bit units.
Input
-A
Notes 1. 2.
Circuit types enclosed in brackets indicate the Schmitt trigger input. BP0 through BP7 select VLC1 as an input source. However, the output levels change depending on the external circuit of BP0 through BP7 and VLC1.
Example
Because BP0 through BP7 are mutually connected inside the PD753017A, the output levels of BP0 through BP7 are determined by R1, R2, and R3.
PD753017A
VDD
R2 BP0 ON VLC1
R1 ON
BP1
R3
10
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
3.2 Non-port Pins (1/2)
Alternate Function P13 P12/INT2 I/O Circuit Type Note 1 -C
Pin Name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ
I/O Input
Function Inputs external event pulses to the timer/event counter.
After Reset Input
Output
P20 P21 P22/PCL P22/PTO2 P23
Timer/event counter output
Input
E-B
Clock output Optional frequency output (for buzzer output or system clock trimming) Serial clock input/output Serial data output Serial data bus input/output Serial data input Serial data bus input/output Edge detection vectored interrupt input (both rising edge and falling edge detection)
Edge detection vectored interrupt input (detection edge can be selected) INT0/P10 can select noise elimination circuit. Rising edge detection testable input Noise elimination circuit/asynchronous selection Asynchronous Asynchronous
SCK SO/SB0
I/O
P01 P02
Input
-A -B
SI/SB1
P03
-C
INT4
Input
P00
Input

INT0
Input
P10
Input
-C
INT1 INT2 KR0-KR3 KR4-KR7 S0-S23 S24-S31 COM0-COM3 VLC0-VLC2 Input Input Input Output Output Output -
P11 P12/TI1/TI2 P60-P63 P70-P73 - BP0-BP7 - -
Input Input Input Note 2 Note 2 Note 2 -
-C -A -A G-A H-A G-B -
Falling edge detection testable input Falling edge detection testable input Segment signal output Segment signal output Common signal output LCD drive power On-chip split resistor is enable (mask option). Output for external split resistor disconnect Clock output for externally expanded driver Clock output for externally expanded driver synchronization
BIAS LCDCL Note 4 SYNC Note 4
Output Output Output
- P30 P31
Note 3 Input Input
- E-B E-B
Notes 1. 2. 3. 4.
Circuit types enclosed in brackets indicate the Schmitt trigger input. Each display output selects the following VLCX as input source. S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0 When a split resistor is contained ....... Low level When no split resistor is contained ..... High impedance These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31.
Data Sheet U11662EJ2V0DS00
11
PD753012A, 753016A, 753017A
3.2 Non-port Pins (2/2)
Alternate Function - - I/O Circuit Type Note -
Pin Name X1 X2
I/O Input -
Function Crystal/ceramic connection pin for the mainsystem clock oscillation. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. System reset input (low level active) Internally connected. Connect directly to VDD. Positive power supply GND
After Reset -
XT1 XT2
Input -
-
-
-
RESET IC VDD VSS
Input - - -
- - - -
- - - -
- - -
Note
Circuit types enclosed in brackets indicate the Schmitt trigger input.
12
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
3.3 Pin Input/Output Circuits
The PD753017A pin input/output circuits are shown schematically.
TYPE A TYPE D VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT
CMOS standard input buffer TYPE B
Push-pull output that can be placed in output high impedance (both P-ch and N-ch off). TYPE E-B VDD P.U.R. P.U.R. enable data Type D output disable P-ch
IN
IN/OUT
Schmitt trigger input with hysteresis characteristics
Type A
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A VDD VDD P.U.R. P.U.R. enable P.U.R. enable data output disable IN Type B Type D P.U.R. P-ch
P-ch
IN/OUT
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Data Sheet U11662EJ2V0DS00
13
PD753012A, 753016A, 753017A
TYPE F-B
VDD P.U.R. P.U.R. enable P-ch VDD P-ch IN/OUT
TYPE H-A
output disable (P) data output disable output disable (N)
SEG data
TYPE G-A
OUT
N-ch
Bit Port data output disable TYPE D
P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P.U.R. VLC1 P-ch N-ch P.U.R. enable P-ch IN/OUT OUT SEG data N-ch VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-D VDD P.U.R. (Mask Option) IN/OUT data P-ch N-ch output disable input instruction N-ch (+13 V withstand voltage) data output disable
N-ch
VLC0 VLC1
VDD P-ch P.U.R.
OUT COM or SEG data N-ch VLC2 N-ch P-ch
Note
Voltage limitation circuit (+13 V withstand voltage) Note The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low).
14
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
3.4 Recommended Connection for Unused Pins
Table 3-1. List of Recommended Connection for Unused Pins
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0, P11/INT1 P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS XT1 XT2Note IC Connect to VSS Only if all of VLC0-VLC2 are unused, connect to VSS. In other cases, leave open. Connect to VSS Leave open Connect to VDD directly Input: Connect to VSS Output: Connect to VSS (do not connect a pull-up resistor of mask option) Input: Connect to VSS or VDD via a resistor individually Output: Leave open Leave open Input: Connect to VSS or VDD via a resistor individually Output: Leave open Connect to VSS Connect to VSS or VDD Connect to VSS or VDD Connect to VSS or VDD via a resistor individually Recommended Connection
Note
When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor).
Data Sheet U11662EJ2V0DS00
15
PD753012A, 753016A, 753017A
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode
The CPU of PD753017A has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). * Mk I mode: * Mk II mode: Upward compatible with PD75316B. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. Incompatible with PD75316B. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I Mode Program memory (bytes) * PD753012A : 12288 * PD753016A, 753017A : 16384 Mk II Mode * PD753012A : 12288 * PD753016A : 16384 * PD753017A : 24576 3 bytes
Number of stack bytes for subroutine instructions BRA !addr1 instruction CALLA !addr1 instruction CALL !addr instruction CALLF !faddr instruction
2 bytes
Not available
Available
3 machine cycles 2 machine cycles
4 machine cycles 3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility.
16
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10XXBNote at the beginning of a program. When using the Mk II mode, it must be initialized to 00XXBNote. Note Set the desired value in the XX positions. Figure 4-1. Stack Bank Select Register Format
Address F84H
3 SBS3
2
1
0 SBS0
Symbol SBS
SBS2 SBS1
Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
0
Be sure to set bit 2 to 0.
Mode switching specification 0 1 Mk II mode Mk I mode
Caution
Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode.
Data Sheet U11662EJ2V0DS00
17
PD753012A, 753016A, 753017A
5. MEMORY CONFIGURATION
* Program memory (ROM) ............... 12288 x 8 bits (PD753012A) ............... 16384 x 8 bits (PD753016A) ............... 24576 x 8 bits (PD753017A) * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. * Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. * Addresses 0020H to 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1byte instructions. It is used to decrease the number of program steps. * Data memory (RAM) * * Data area ...1024 words x 4 bits (000H to 3FFH) Peripheral hardware area...128 x 4 bits (F80H to FFFH)
18
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Figure 5-1. Program Memory Map (1/3) (a) PD753012A
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
0008H
MBE
RBE
INTCSI start address INTCSI start address
BRCB !caddr instruction branch address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (-15 to -1, +2 to +16)
0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH Branch destination address and subroutine entry address when GETI instruction is executed
BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction.
Data Sheet U11662EJ2V0DS00
19
PD753012A, 753016A, 753017A
Figure 5-1. Program Memory Map (2/3) (b) PD753016A
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction subroutine entry address CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
0008H
MBE
RBE
INTCSI start address INTCSI start address
BRCB !caddr instruction branch address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (-15 to -1, +2 to +16) GETI instruction reference table
0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH
Branch destination address and subroutine entry address when GETI instruction is executed
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction.
20
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Figure 5-1. Program Memory Map (3/3) (c) PD753017A
7 0000H MBE 6 RBE 5 0
Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits)
0002H
MBE
RBE
INTBT/INT4 start address INTBT/INT4 start address
(high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) (high-order 6 bits) (Iow-order 8 bits) CALL !addr instruction branch address Branch address of BR BCDE, GETI instruction BR BCXA, branch/call BRA !addr1Note or address CALLA !addr1Note instruction BR !addr instruction branch address CALLF !faddr instruction entry address
0004H
MBE
RBE
INT0 start address INT0 start address
0006H
MBE
RBE
INT1 start address INT1 start address
BRCB !caddr instruction branch address
0008H
MBE
RBE
INTCSI start address INTCSI start address
000AH
MBE
RBE
INTT0 start address INTT0 start address
000CH
MBE
RBE
INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits)
0020H GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H 5FFFH
BR $addr1 instruction relative branch address (-15 to -1, +2 to +16)
BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address
Note Can be used only in the Mk II mode. Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H3FFFH). Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction.
Data Sheet U11662EJ2V0DS00
21
PD753012A, 753016A, 753017A
Figure 5-2. Data Memory Map
Data memory 000H General purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (224 x 4) 1DFH 1E0H Display data memory Stack areaNote Data area static RAM (1024 x 4) 256 x 4 2 1FFH 200H (32 x 4) 1 (32 x 4) Memory bank
2FFH 300H
256 x 4
3
3FFH
Not incorporated
F80H
Peripheral hardware area
128 x 4
15
FFFH
Note For stack area, one memory bank can be selected among memory banks 0 to 3.
22
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input/Output Ports
There are four types of I/O ports as follows. * CMOS input (PORT0, 1) * CMOS input/output (PORT2, 3, 6, 7) * N-channel open-drain input/output (PORT4, 5) * Bit port output (BP0-BP7) Total : : : 8 8 8 40 Table 6-1. Types and Features of Digital Ports
Port (Pin Name) PORT0 (P00-P03) Function 4-bit input Operation and Features When the serial interface function is used, the alternate function pins function as output ports depending on the operation mode. Input-only port Remarks Also used for the INT4, SCK, SO/SB0, SI/SB1 pins.
: 16
PORT1 (P10-P13) PORT2 (P20-P23) PORT3 (P30-P33) PORT4 (P40-P43) PORT5 (P50-P53) PORT6 (P60-P63) 4-bit I/O (N-channel open-drain, 13 V withstanding) 4-bit I/O 4-bit I/O
Also used for the INT0INT2 and TI0-TI2 pins. Also used for the PTO0PTO2, PCL, BUZ pins. Also used for the LCDCL, SYNC pins. On-chip pull-up resistor can be specified bit-wise by mask option.
Can be set to input mode or output mode in 4-bit units.
Can be set to input mode or output mode in 1/4-bit units. Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units.
Can be set to input mode or output mode in 1/4-bit units. Can be set to input mode or output mode in 4-bit units.
Ports 6 and 7 are paired and data can be input/ output in 8-bit units.
Also used for the KR0-KR3 pins.
PORT7 (P70-P73)
Also used for the KR4-KR7 pins.
BP0-BP7
1-bit output
Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 by software.
--
Data Sheet U11662EJ2V0DS00
23
PD753012A, 753016A, 753017A
6.2 Clock Generator
Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The two clocks, the main system clock and subsystem clock, are available. The instruction excution time can be altered. * 0.95 s, 1.91 s, 3.81 s, 15.3 s (main system clock : at 4.19 MHz operation) * 0.67 s, 1.33 s, 2.67 s, 10.7 s (main system clock : at 6.0 MHz operation) * 122 s (subsystem clock : at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram
* Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * LCD controller/driver * INT0 noise elimination circuit * Clock output circuit 1/1 to 1/4096 Divider 1/2 1/4 1/16
XT1 VDD XT2 X1 VDD X2 Main system clock oscillator fX Subsystem clock oscillator fXT LCD controller/driver Watch timer
Selector WM.3 SCC SCC3 Oscillation stop Selector
Divider 1/4 * CPU * INT0 noise elimination circuit * Clock output circuit
Internal bus
SCC0 PCC PCC0 PCC1 4 PCC2 HALTNote STOPNote PCC3 R Q HALT F/F S
PCC2, PCC3 Clear
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note Instruction execution Remarks 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock PCC: Processor Clock Control Register SCC: System Clock Control Register One clock cycle (tCY) of equal to one machine cycle of the instruction.
Data Sheet U11662EJ2V0DS00
24
PD753012A, 753016A, 753017A
6.3 Subsystem Clock Oscillator Control Functions
The PD753017A subsystem clock oscillator has the following two control functions. * Selects by software whether an internal feedback resistor is to be used or notNote. * Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor) by software, connect XT1 to VSS, and open XT2. This makes it possible to reduce the current consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator
SOS.0
Feedback resistor Inverter SOS.1 XT1 XT2
VDD
Data Sheet U11662EJ2V0DS00
25
PD753012A, 753016A, 753017A
6.4 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL pin to the application of remote control wave outputs and peripheral LSI's. * Clock output (PCL) : , 524, 262, 65.5 kHz (at 4.19 MHz operation) , 750, 375, 93.8 kHz (at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram
From clock generator fX/23 Selector fX/24 fX/26 From timer/event counter (channel 2)
Selector
Output buffer PCL/PTO2/P22
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch
Bit 2 of PMGB Port 2 I/O mode specification bit
4 Internal bus
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable.
26
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
6.5 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions. * Interval timer operation to generate a reference time interrupt * Watchdog timer operation to detect a runaway of program and reset the CPU * Selects and counts the wait time when the standby mode is released * Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram
From clock generator fX/25 fX/27 MPX fX/29 fX/212 3 BT Clear Clear
Basic interval timer (8-bit frequency divider)
Set
BT interrupt request flag Vectored interrupt IRQBT request signal
Wait release signal when standby is released.
Internal reset signal WDTM SET1Note 1
BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 8 Internal bus
Note Instruction execution
Data Sheet U11662EJ2V0DS00
27
PD753012A, 753016A, 753017A
6.6 Watch Timer
The PD753017A has one channel of watch timer. The watch timer has the following functions. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. * 0.5 sec interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). * Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. * Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of system clock oscillation frequencies. * Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram
fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) fXT (32.768 kHz) Selector
fLCD
fW (32.768 kHz) 4 kHz 2 kHz fW fW 23 24
Divider
fW 214 2 Hz 0.5 sec
Selector INTW IRQW set signal
Clear
Selector
Output buffer P23/BUZ
WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3 P23 output latch
PMGB bit 2 Port 2 input/ output mode
8
Bit test instruction
Internal bus
The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz.
28
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
6.7 Timer/Event Counter
The PD753017A has three channels of timer/event counter. The timer/event counter has the following functions. * Programmable interval timer operation * Square wave output of any frequency to the PTOn pin (n = 0, 1) * Event counter operation * Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency division operation). * Supplies the shift clock to the serial interface circuit (channel 0 only). * Calls the count value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter
Channel Channel 0 Mode 8-bit timer/event counter mode Gate control function PWM pulse generator mode 16-bit timer/event counter mode Gate control function Carrier generator mode Yes NoNote No No NoNote No Yes No No Yes Yes Yes Yes Yes Yes Channel 1 Channel 2
Note Used for gate control signal generation
Data Sheet U11662EJ2V0DS00
29
30
8 - PORT1.3 Input buffer TI0 fX/24
From clock generator
Figure 6-6. Timer/Event Counter Block Diagram (Channel 0)
Internal bus SET1 TM0 TM06 TM05 TM04 TM03 TM02 - - 8 8 TMOD0 Modulo register (8)
TOE0 TO enable flag
PORT2.0 PMGB bit 2 Port 2 P20 input/output output latch mode To serial interface
8 TOUT0 Comparator (8) 8 Reset T0 MPX Count register (8) CP Clear Match TOUT F/F
P20/PTO0 Output buffer
Data Sheet U11662EJ2V0DS00
fX/26 fX/28 fX/210 Timer operation start
INTT0 IRQT0 set signal
RESET IRQT0 clear signal
PD753012A, 753016A, 753017A
To timer/event counter (channel 2)
Figure 6-7. Timer/Event Counter Block Diagram (Channel 1)
Internal bus 8 TM1 - TM16 TM15 TM14 TM13 TM12 TM11 TM10 Decoder 8 TMOD1 PORT1.2 Modulo register (8) 8 Input buffer TI1/TI2/P12/INT2
Data Sheet U11662EJ2V0DS00
TOE1 T1 enable flag
PORT2.1 P21 output latch
PMGB.2
Port 2 input/output mode
Comparator (8) 8 MPX CP Count register (8) Clear T1
Match
TOUT F/F Reset
P21/PTO1 Output buffer
Timer/event counter output (channel 2) fX/25 fX/26 From clock 8 generator fX/2 fX/210 fX/212
PD753012A, 753016A, 753017A
RESET Timer operation start 16-bit timer/event counter mode Selector IRQT1 clear signal
Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode)
Timer/event counter reload signal (channel 2)
INTT1 IRQT1 set signal
Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode)
31
Selector
Selector
TI1/TI2/ P12/INT2
Data Sheet U11662EJ2V0DS00
fX fX/2 From clock fX/24 generator fX/26 fX/28 fX/210
MPX
CP
T2 Count register (8) Clear
8
Reset Overflow Carrier generator mode
Selector
32
8 TM2
TM26 TM25 TM24 TM23 TM22 TM21 TM20
Figure 6-8. Timer/Event Counter Block Diagram (Channel 2)
Internal bus 8 TMOD2H
Modulo register for high level period setup (8)
8 TMOD2
TGCE
8 TC2
TOE2 REMC NRZB NRZ
Reload
PORT1.2 Decoder
8
Modulo register (8) 8
PORT2.2 PMGB.2 P22 Port 2 output latch input/output
P22/PCL/PTO2
MPX (8) 8 Comparator (8)
Match
Input buffer
TOUT F/F
Output buffer
Timer/event counter clock input (channel 1)
16-bit timer/event counter mode
INTT2 IRQT2 set signal IRQT2 clear signal
Timer operation start
RESET
PD753012A, 753016A, 753017A
Timer event counter TOUT F/F (channel 0)
Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) From clock output circuit
PD753012A, 753016A, 753017A
6.8 Serial Interface
The PD753017A is provided with an 8-bit clocked serial interface. This serial interface operates in the following four modes: * Operation stop mode * 3-wire serial I/O mode * 2-wire serial I/O mode * SBI mode
Data Sheet U11662EJ2V0DS00
33
ACKE
P02/SO/SB0
Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
ACKT
34
8/4 Bit test CSIM P03/SI/SB1 Selector
Data Sheet U11662EJ2V0DS00
Figure 6-9. Serial Interface Block Diagram
Internal bus 8 8 8 Bit manipulation SBIC RELT CMDT (8) SET CLR Shift register (SIO) (8) D Q SO latch Bit test
Slave address register (SVA) (8) Match signal Address comparator
PD753012A, 753016A, 753017A
P01/SCK Serial clock counter
INTCSI INTCSI control circuit IRQCSI set signal fX/23 fX/24 fX/26 TOUT0 (from timer/ event counter 0)
P01 output Iatch
Serial clock control circuit
Serial clock selector
External SCK
PD753012A, 753016A, 753017A
6.9 LCD Controller/Driver
The PD753017A incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The PD753017A LCD controller/driver functions are as follows: * Display data memory is read automatically by DMA operation and segment and common signals are generated. * Display mode can be selected from among the following five: 1 Static 2 1/2 duty (time multiplexing by 2), 1/2 bias 3 1/3 duty (time multiplexing by 3), 1/2 bias 4 1/3 duty (time multiplexing by 3), 1/3 bias 5 1/4 duty (time multiplexing by 4), 1/3 bias * A frame frequency can be selected from among four in each display mode. * A maximum of 32 segment signal output pins (S0-S31) and four common signal output pins (COM0-COM3). * The segment signal output pins (S24-S27 and S28-S31) can be changed to the output ports in 4-pin units. * Split-resistor can be incorporated to supply LCD drive power (mask option). * Various bias methods and LCD drive voltages can be applicable. * When display is off, current flow to the split resistor is cut. * Display data memory not used for display can be used for normal data memory. * It can also operate by using the subsystem clock.
Data Sheet U11662EJ2V0DS00
35
Segment driver
Common driver
LCD drive voltage control
S31/BP7
S30/BP6
S24/BP0
S23
S0
COM3 COM2 COM1 COM0
VLC2
VLC1
VLC0
LCD drive mode changer
36
4 Display data memory 1FFH 32 10 1FEH 32 10 32 10 32 10
Data Sheet U11662EJ2V0DS00
Figure 6-10. LCD Controller/Driver Block Diagram
Internal bus 8 1F8H 32 10 1E0H 32 10 4
Display control register
4 Port 3 output latch 10
8
Port mode register group A
1F9H 32 10
Display mode register
10
32 10
32 10
32 10
Timing controller
fLCD
Multiplexer
PD753012A, 753016A, 753017A
Selector
P31/ P30/ SYNC LCDCL
PD753012A, 753016A, 753017A
6.10 Bit Sequential Buffer ... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format
Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0
BSB3
BSB2
BSB1
BSB0
L register
L = FH
L = CH
L = BH
L = 8H
L = 7H
L = 4H DECS L
L = 3H
L = 0H
INCS L
Remarks 1. 2.
In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
Data Sheet U11662EJ2V0DS00
37
PD753012A, 753016A, 753017A
7. INTERRUPT FUNCTION AND TEST FUNCTION
PD753017A has eight types of interrupt sources and two types of test sources. Among the test sources, INT2
is provided with two testable inputs for edge detection.
PD753017A has the following functions in the interrupt control circuit.
(1) Interrupt function * Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IEXXX) and interrupt master enable flag (IME). * Can set any interrupt start address. * Nesting interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). * Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software. * Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function * Test request flag (IRQXXX) generation can be checked by software. * Release the standby mode. The test source to be released can be selected by the test enable flag.
38
Data Sheet U11662EJ2V0DS00
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus 2 1 4 IME IPS IM2 IM1 IM0 Interrupt enable flag (IExxx) Decoder INTBT INT4/P00 INT0/P10 INT1/P11
Note
Selector
IST1
IST0
IRQBT
VRQn
Both edge detector Edge detector Edge detector INTCSI INTT0 INTT1 INTT2 INTW
IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQT1 Priority control circuit Vector table address generator
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
IRQT2 IRQW IRQ2 Standby release signal
INT2/P12
Rising edge detector
Selector
KR0/P60 KR3/P63
Falling edge detector
IM2
Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.)
39
PD753012A, 753016A, 753017A
8. STANDBY FUNCTION
In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the PD753017A. Table 8-1. Operation Status in Standby Mode
STOP Mode Set instruction System clock when set STOP instruction Settable only when the main system clock is used. Only the main system clock stops oscillation. Operation stops HALT Mode HALT instruction Settable both by the main system clock and subsystem clock. Only the CPU clock halts (oscillation continues). Operation. (The IRQBT is set in the reference interval.)Note 1 OperableNote 1
Operation status
Clock generator
Basic interval timer/ watchdog timer Serial interface
Operable only when an external SCK input is selected as the serial clock. Operable only when a signal input to the TI0-TI2 pins is specified as the count clock. Operable when fXT is selected as the count clock. Operable only when fXT is selected as the LCDCL. The INT1, 2, and 4 are operable. Only the INT0 is not operated.Note 2 The operation stops.
Timer/event counter
OperableNote 1
Watch timer
Operable
LCD controller/driver
Operable
External interrupt
CPU Release signals
* Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. * Test request signal sent from the test source enabled by the test enable flag. * RESET input
Notes 1. 2.
Cannot operate only when the main system clock stops. Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0).
40
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
9. RESET FUNCTION
There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function
RESET
Internal reset signal
Reset signal sent from the basic interval timer/watchdog timer WDTM
Internal bus
The PD753017A is set by the RESET signal generated and each hardware is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation
Wait Note
RESET signal generated Operation mode or standby mode HALT mode Internal reset operation Operation mode
Note
The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation)
Data Sheet U11662EJ2V0DS00
41
PD753012A, 753016A, 753017A
Table 9-1. Status of Each Hardware after Reset (1/2)
RESET Signal Generation in Standby Mode Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Resets the PC14 of the PD753017A to 0. Held 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Held Held 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH RESET Signal Generation in Operation Sets the low-order 6 bits of program memory's address 0000H to the PC13-PC8 and the contents of address 0001H to the PC7-PC0. Resets the PC14 of the PD753017A to 0. Undefined 0 0 Sets the bit 6 of program memory's address 0000H to the RBE and bit 7 to the MBE. Undefined 1000B Undefined Undefined 0, 0 Undefined 0 0 0 FFH 0 0, 0 0 FFH 0 0, 0 0 FFH FFH
Hardware Program counter (PC)
PSW
Carry flag (CY) Skip flag (SK0-SK2) Interrupt status flag (IST0) Bank enable flag (MBE, RBE)
Stack pointer (SP) Stack bank select register (SBS) Data memory (RAM) General-purpose register (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Basic interval timer/ watchdog timer Timer/event counter (T0) Counter (BT) Mode register (BTM) Watchdog timer enable flag (WDTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/event counter (T1) Counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event counter (T2) Counter (T2) Modulo register (TMOD2) High level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB TGE Watch timer Mode register (WM)
0 0, 0 0, 0, 0 0 0
0 0, 0 0, 0, 0 0 0
42
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Table 9-1. Status of Each Hardware after Reset (2/2)
RESET Signal Generation in Standby Mode Held 0 0 Held 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Held RESET Signal Generation in Operation Undefined 0 0 Undefined 0 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 0 Off Cleared (0) 0 0 Undefined
Hardware Serial interface Shift register (SIO) Operation mode register (CSIM) SBI control register (SBIC) Slave address register (SVA) Clock generator, clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM)
Sub-oscillator control register (SOS) LCD controller/ driver Interrupt function Display mode register (LCDM) Display control register (LCDC) Interrupt request flag (IRQXXX) Interrupt enable flag (IEXXX) Interrupt master enable flag (IME) INT0, 1, 2 mode registers (IM0, IM1, IM2) Interrupt priority selection register (IPS) Digital port Output buffer Output latch I/O mode registers (PMGA, PMGB) Pull-up resistor specification register (POGA) Bit sequential buffer (BSB0-BSB3)
Data Sheet U11662EJ2V0DS00
43
PD753012A, 753016A, 753017A
10. MASK OPTION
The PD753017A has the following mask options.
* P40-P43, P50-P53 mask options
On-chip pull-up resistors can be connected. <1> On-chip pull-up resistors are specifiable bit-wise. <2> On-chip pull-up resistors are not specifiable.
* VLC0-VLC2 pins, BIAS pin mask option
On-chip split resistor for LCD drive can be connected. <1> Split resistor is not connected. <2> Four 10 k (TYP.) split resistors are connected at the same time. <3> Four 100 k (TYP.) split resistors are connected at the same time.
* Standby function mask option
Wait times can be selected by a RESET signal. <1> 2 17/fX (21.8 ms : at fX = 6.0 MHz, 31.3 ms : at fX = 4.19 MHz) <2> 215/fX (5.46 ms : at fX = 6.0 MHz, 7.81 ms : at fX = 4.19 MHz)
* Subsystem clock mask option
Use of the internal feedback resistor can be selected. <1> Internal feedback resistor can be used. (Switched ON/OFF via software) <2> Internal feedback resistor cannot be used. (Switched out in hardware)
44
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
11. INSTRUCTION SET
(1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to RA75X Assembler Package User's Manual----Language (U12385E). If there are several elements, one of them is selected. Capital letters and the + and - symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see User's Manual.
Expression Format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, BC, XA, BC, DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL'
Description Method
HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-2FFFH immediate data or label (PD753012A) 0000H-3FFFH immediate data or label (PD753016A, 753017A) 0000H-5FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (where bit0 = 0) or label PORT0-PORT7 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB3, MB15
Note
mem can be only used even address in 8-bit data processing.
Data Sheet U11662EJ2V0DS00
45
PD753012A, 753016A, 753017A
(2) Legend in explanation of operation A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : XA register pair; 8-bit accumulator : BC register pair : DE register pair : HL register pair : XA' expanded register pair : BC' expanded register pair : DE' expanded register pair : HL' expanded register pair : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Port n (n = 0-7) : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Separation between address and bit : The contents addressed by XX : Hexadecimal data
46
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
(3) Explanation of symbols under addressing area column
*1 MB = MBE*MBS (MBS = 0-3, 15) MB = 0 MBE = 0 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-3, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH
*2 *3
Data memory addressing
*4 *5 *6
PD753012A PD753016A 753017A
addr = 0000H-2FFFH addr = 0000H-3FFFH
*7
PD753012A 753016A 753017A (In Mk I mode) PD753017A (In Mk II mode)
addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH (PC13, 12 = 00B) or 1000H-1FFFH (PC13, 12 = 01B) or 2000H-2FFFH (PC13, 12 = 10B) caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5FFFH (PC13, 12 (PC13, 12 (PC13, 12 (PC13, 12 = = = = 00B) or 01B) or 10B) or 11B) = = = = = = 000B) 001B) 010B) 011B) 100B) 101B) or or or or or
*8
PD753012A
PD753016A
Program memory addressing
PD753017A
(PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12
*9 *10 *11
faddr = 0000H-07FFH taddr = 0020H-007FH
PD753012A PD753016A PD753017A
addr1 = 0000H-2FFFH addr1 = 0000H-3FFFH addr1 = 0000H-5FFFH
Remarks 1. 2. 3. 4.
MB indicates memory bank that can be accessed. In *2, MB = 0 independently of how MBE and MBS are set. In *4 and *5, MB = 15 independently of how MBE and MBS are set. *6 to *11 indicate the areas that can be addressed.
Data Sheet U11662EJ2V0DS00
47
PD753012A, 753016A, 753017A
(4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. * When no skip is made: S = 0 * When the skipped instruction is a 1- or 2-byte instruction: S = 1 * When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC.
48
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Number of Machine Cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg1 XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L+1 A (HL), then L L-1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH String effect A String effect B
Instruction Group Transfer
Mnemonic
Operand
Number of Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2
Operation
Addressing Area
Skip Condition
MOV
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA
String effect A
XCH
A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp'
Data Sheet U11662EJ2V0DS00
49
PD753012A, 753016A, 753017A
Number of Machine Cycles 3
Instruction Group Table reference
Mnemonic
Operand
Number of Bytes 1
Operation XA (PC13-8+DE)ROM
q PD753017A
Addressing Area
Skip Condition
MOVTNote 1
XA, @PCDE
XA (PC14-8+DE)ROM
XA, @PCXA
1
3
XA (PC13-8+XA)ROM
q PD753017A
XA (PC14-8+XA)ROM *6 *11
XA,
@BCDENote 2
1
3
XA (B1,0+CDE)ROM
q PD753017A
XA (B2-0+CDE)ROM *6 *11
XA, @BCXANote 2
1
3
XA (B1,0+CXA)ROM
q PD753017A
XA (B2-0+CXA)ROM *4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
Bit transfer
MOV1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY
2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2
2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2
CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A+n4 XA XA+n8 A A+(HL) XA XA+rp' rp'1 rp'1+XA A, CY A+(HL)+CY XA, CY XA+rp'+CY rp'1, CY rp'1+XA+CY A A-(HL) XA XA-rp' rp'1 rp'1-XA A, CY A-(HL)-CY XA, CY XA-rp'-CY rp'1, CY rp'1-XA-CY
Operation
ADDS
A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA
ADDC
A, @HL XA, rp' rp'1, XA
SUBS
A, @HL XA, rp' rp'1, XA
*1
borrow borrow borrow
SUBC
A, @HL XA, rp' rp'1, XA
*1
Notes 1. 2.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Only the following bits are valid for the B register.
PD753012A, 753016A : low-order 2 bits PD753017A
: low-order 3 bits
Remark When the PD753017A is set in the Mk I mode, PC14 is fixed to 0.
50
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Number of Machine Cycles 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A v n4 A A v (HL) XA XA v rp' rp'1 rp'1 v XA CY A0, A3 CY, An-1 An AA reg reg+1 rp1 rp1+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 rp' rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY CY = 1 *1 *1 *1 *1 *3 reg = 0 rp1 = 00H (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' *1 *1 *1
Instruction Group Operation
Mnemonic
Operand
Number of Bytes 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
Operation
Addressing Area
Skip Condition
AND
A, #n4 A, @HL XA, rp' rp'1, XA
OR
A, #n4 A, @HL XA, rp' rp'1, XA
XOR
A, #n4 A, @HL XA, rp' rp'1, XA
Accumulator manipulation
RORC NOT
A A reg rp1 @HL mem
Increment and Decrement
INCS
DECS
reg rp'
Comparison
SKE
reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY
Data Sheet U11662EJ2V0DS00
51
PD753012A, 753016A, 753017A
Number of Machine Cycles 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit)=1 Skip if (fmem.bit)=1 Skip if (pmem7-2+L3-2.bit(L1-0))=1 Skip if (H+mem3-0.bit)=1 Skip if (mem.bit)=0 Skip if (fmem.bit)=0 Skip if (pmem7-2+L3-2.bit(L1-0))=0 Skip if (H+mem3-0.bit)=0 Skip if (fmem.bit)=1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY v (fmem.bit) CY CY v (pmem7-2+L3-2.bit(L1-0)) CY CY v (H+mem3-0.bit)
Instruction Group Memory bit manipulation
Mnemonic
Operand
Number of Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
SET1
mem.bit fmem.bit pmem.@L @H+mem.bit
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
(mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR
fmem.bit pmem.@L @H+mem.bit
AND1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
OR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
XOR1
CY, fmem.bit CY, pmem.@L CY, @H+mem.bit
52
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Number of Machine Cycles -
Instruction Group Branch
Mnemonic
Operand
Number of Bytes -
Operation PC13-0 addr Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRCB !caddr BR $addr
q PD753012A, 753016A PC13-0 addr1 Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr1 q PD753017A PC14-0 addr1 Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr1
Addressing Area *6
Skip Condition
BRNote 1
addr
addr1
-
-
*11
!addr
3
3
PC13-0 addr
q PD753017A PC14 0, PC13-0 addr
*6
$addr $addr1
1 1
2 2
PC13-0 addr
q PD753017A PC14-0 addr1
*7
PCDE
2
3
PC13-0 PC13-8+DE
q PD753017A PC14-0 PC14-8+DE
PCXA
2
3
PC13-0 PC13-8+XA
q PD753017A PC14-0 PC14-8+XA
BCDENote 2
2
3
PC13-0 BCDE
q PD753017A PC14-0 BCDE
*6 *11
BCXANote 2
2
3
PC13-0 BCXA
q PD753017A PC14-0 BCXA
*6 *11
Notes 1. 2.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Only the following bits are valid for the B register.
PD753012A, 753016A : low-order 2 bits PD753017A
: low-order 3 bits
Remark When the PD753017A is set in the Mk I mode, PC14 is fixed to 0.
Data Sheet U11662EJ2V0DS00
53
PD753012A, 753016A, 753017A
Number of Machine Cycles 3
Instruction Group Branch
Mnemonic
Operand
Number of Bytes 3
Operation
q PD753012A, 753016A PC13-0 addr q PD753017A PC14-0 addr1
Addressing Area *6
Skip Condition
BRANote
!addr
!addr1
3
3
*11
BRCBNote
!caddr
2
2
PC13-0 PC13,12+caddr11-0
q PD753017A PC14-0 PC14,13,12+caddr11-0
*8
Subroutine stack control
CALLANote
!addr
3
3
q PD753012A, 753016A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, 0, PC13, 12 (SP-2) x, x, MBE, RBE PC13-0 addr, SP SP-6 q PD753017A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, PC14, 13, 12 (SP-2) x, x, MBE, RBE PC14-0 addr1, SP SP-6
*6
!addr1
3
3
*11
CALLNote
!addr
3
3
(SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP-4
q PD753012A, 753016A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, 0, PC13, 12 (SP-2) x, x, MBE, RBE PC13-0 addr, SP SP-6 q PD753017A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, PC14, 13, 12 (SP-2) x, x, MBE, RBE PC14 0, PC13-0 addr, SP SP-6
*6
4
4
CALLFNote
!faddr
2
2
(SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 000+faddr, SP SP-4
q PD753012A, 753016A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, 0, PC13, 12 (SP-2) x, x, MBE, RBE PC13-0 000+faddr, SP SP-6 q PD753017A (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, PC14, 13, 12 (SP-2) x, x, MBE, RBE PC14-0 0000+faddr, SP SP-6
*9
3
3
Note
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Remark When the PD753017A is set in the Mk I mode, PC14 is fixed to 0.
54
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Number of Machine Cycles 3
Instruction Group Subroutine stack control
Mnemonic
Operand
Number of Bytes 1
Operation MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4
q PD753012A, 753016A x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 q PD753017A x, x, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6
Addressing Area
Skip Condition
RETNote
RETSNote
1
3+S
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+4 then skip unconditionally
q PD753012A, 753016A x, x, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally q PD753017A x, x, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally
Unconditional
RETINote
!faddr
1
3
MBE, RBE, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
q PD753012A, 753016A 0, 0, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 q PD753017A 0, PC14, PC13, PC12 (SP+1) PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6
Note
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode.
Remark When the PD753017A is set in the Mk I mode, PC14 is fixed to 0.
Data Sheet U11662EJ2V0DS00
55
PD753012A, 753016A, 753017A
Number of Machine Cycles 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3
Instruction Group Subroutine stack control
Mnemonic
Operand
Number of Bytes 1 2 1 2 2
Operation (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) RBS, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), RBS (SP), SP SP+2 IME(IPS.3) 1 IEXXX 1 IME(IPS.3) 0 IEXXX 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT mode (PCC.2 1) Set STOP mode (PCC.3 1) No operation RBS n MBS n (n = 0-3) (n = 0-3, 15) (n = 0-7) (n = 4, 6) (n = 2-7) (n = 4, 6)
Addressing Area
Skip Condition
PUSH
rp BS
POP
rp BS
Interrupt control
EI IEXXX DI IEXXX
2 2 2 2 2 2 2 2 2 1
Input/output
INNote 1
A, PORTn XA, PORTn
OUTNote 1
PORTn, A PORTn, XA
CPU control
HALT STOP NOP
Special
SEL
RBn MBn
2 2 1
GETINotes 2, 3
taddr
* When TBR instruction PC13-0 (taddr)5-0+(taddr+1) * When TCALL instruction (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 (taddr)5-0+(taddr+1) SP SP-4 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed
*10
Depending on the reference instruction
1
3
PD753017A * When TBR instruction PC13-0 (taddr)5-0+(taddr+1) PC14 0
q
4
* When TCALL instruction (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0, 0, PC13, 12 (SP-2) x, x, MBE, RBE PC13-0 (taddr)5-0+(taddr+1) SP SP-6, PC14 0 * When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed Depending on the reference instruction
3
Notes 1. 2. 3.
While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction.
Remark When the PD753017A is set in the Mk I mode, PC14 is fixed to 0.
56
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Other than ports 4, 5 Ports 4, 5 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Pull-up resistor provided N-ch open-drain Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +14 -0.3 to VDD + 0.3 -10 -30 30 220 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Data Sheet U11662EJ2V0DS00
57
PD753012A, 753016A, 753017A
Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Circuit
Resonator Ceramic resonator
Parameter Oscillation frequency (fX)Note 1
Conditions
MIN. 1.0
TYP.
MAX. 6.0Note 2
Unit MHz
X1
X2
C1 VDD Crystal resonator
C2
Oscillation stabilization timeNote 3
After VDD has reached MIN. value of oscillation voltage range 1.0
4
ms
X1
X2
Oscillation frequency (fX)Note 1
6.0Note 2
MHz
C1 VDD
C2
Oscillation stabilization timeNote 3
VDD = 4.5 to 5.5 V
10 30
ms
External clock
X1
X2
X1 input frequency (fX)Note 1
1.0
6.0Note 2
MHz
X1 input high-, low-level width (tXH, tXL)
83.3
500
ns
Notes 1. 2.
The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not set the processor clock control register (PCC) to 0011. If PCC = 0011, one machine cycle time is less than 0.95 s, falling short of the rated value of 0.95 s.
3.
The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released.
Caution When using the main system clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillator.
58
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Recommended Oscillator Constant Ceramic resonator (TA = -20 to +80C)
Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant (pF) C1 TDK Corp. CCR1000K2 CCR2.0MC33 CCR4.19MC3 FCR4.19MC5 CCR6.0MC3 Murata Mfg. Co., Ltd. CSB1000J Note CSA2.00MG040 CST2.00MG040 CSA4.19MG CST4.19MGW CSA6.00MG CST6.00MGW Kyocera Corp. KBR-1000F/Y KBR-2.0MS KBR-4.0MSA/MSB KBR-4.0MKC KBR-4.0MKD KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-4.19MSA KBR-4.19MSB KBR-4.19MKC KBR-4.19MKD KBR-4.19MKS PBRC4.19A PBRC4.19B KBR-6.0MSA/MSB KBR-6.0MKC KBR-6.0MKD KBR-6.0MKS PBRC6.00A PBRC6.00B 33 - 33 - - On-chip capacitor 6.0 33 - 33 - 33 - 33 - - On-chip capacitor - On-chip capacitor 4.19 4.0 33 - 33 33 - 33 - 33 33 - On-chip capacitor - On-chip capacitor - 1.0 2.0 4.0 6.0 4.19 6.0 1.0 2.0 100 100 - 30 - 30 - 100 68 33 - 100 100 - 30 - 30 - 100 68 33 - On-chip capacitor 1.8 5.5 2.3 1.8 2.1 1.9 5.5 Rd = 5.6 k - On-chip capacitor - On-chip capacitor - On-chip capacitor - 1.0 2.0 4.19 100 - C2 100 - Oscillation Voltage Range (V) MIN. 1.8 MAX. 5.5 - On-chip capacitor Remarks
Data Sheet U11662EJ2V0DS00
59
PD753012A, 753016A, 753017A
Note When using the CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 5.6 k) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended resonators.
X1 CSB1000J C1
X2 Rd
C2
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use.
60
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Recommended Circuit
Resonator Crystal resonator
Parameter Oscillation frequency (fXT)Note 1
Conditions
MIN. 32
TYP. 32.768
MAX. 35
Unit kHz
XT1
XT2 R
C3 VDD
External clock
XT1 XT2
C4
Oscillation stabilization timeNote 2
VDD = 4.5 to 5.5 V
1.0
2 10
ms
XT1 input frequency (fXT)Note 1
32
100
kHz
XT1 input high-, low-level width (tXTH, tXTL)
5
15
s
Notes 1. 2.
The oscillation frequency shown above indicates characteristics of the oscillator only. instruction execution time, refer to AC Characteristics.
For the
The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied.
Caution When using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U11662EJ2V0DS00
61
PD753012A, 753016A, 753017A
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, RESET VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3 VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VIH3 Ports 4, 5 Pull-up resistor provided N-ch open-drain VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, RESET VIL1 X1, XT1 Ports 2, 3, 4, 5 VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VIL3 High-level output voltage Low-level output voltage VOH VOL1 X1, XT1 SCK, SO, Ports 2, 3, 6, 7, BP0-BP7 IOH = -1 mA SCK, SO, Ports 2-7, BP0-BP7 IOL = 15 mA VDD = 5.0 V 10% IOL = 1.6 mA VOL2 SB0, SB1 N-ch open-drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 ILIL3 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1, ports 4, 5 X1, XT1 Ports 4, 5 (N-ch open-drain) Pins other than X1, XT1, ports 4, 5 X1, XT1 Ports 4, 5 (N-ch open-drain) When input instruction is not executed Ports 4, 5 (N-ch open-drain) When input instruction is executed High-level output leakage current ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 7, ports 4, 5 (pull-up resistor provided), BP0-BP7 ILOH2 Low-level output leakage current Internal pull-up resistor RL1 RL2 VIN = 0 V Ports 0, 1, 2, 3, 6, 7 (except P00 pin) Ports 4, 5 (mask option selected) 50 15 100 30 200 60 k k ILOL VOUT = 13 V Ports 4, 5 (N-ch open-drain) VOUT = 0 V 20 -3 3 VDD = 5 V VDD = 3 V -10 -3 -30 -27 -8 3 20 20 -3 -20 -3 0.4 0.2 VDD V V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-0.5 0.2 2.0 Conditions MIN. TYP. MAX. 15 150 VDD VDD VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V V V V
A A A A A A A A A
A
A A
62
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter LCD drive voltageNote 1 VAC current LCD split resistorNote 3 LCD output voltage deviation
Note 4 Note 2
Symbol VLCD VAC0 = 0 VAC0 = 1 IVAC RLCD1 RLCD2 VODC IO = 1.0 A VODS IO = 0.5 A IDD1
Conditions
MIN. 2.2 1.8
TYP.
MAX. VDD VDD
Unit V V
VAC0 = 1, VDD = 2.0 V 10% 50 5 VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 1.8 V VLCD VDD 0 0
1 100 10
4 200 20 0.2
A
k k V
(common) LCD output voltage deviationNote 4 (segment) Supply currentNotes 2, 5 IDD2
6.00 MHzNote 6 crystal oscillation C1 = C2 = 22 pF 4.19 MHz crystal oscillation C1 = C2 = 22 pF
Note 6
0.2
V
VDD = 5.0 V 10%Note 7 VDD = 3.0 V HALT mode 10%Note 8 VDD = 5.0 V 10% VDD = 3.0 V 10%
2.2 0.6 0.72 0.27 1.7 0.3 0.7 0.23 15 8 15 12 12 8.5 4 8.5 3.5 3.5 0.05 0.02
6.6 2.0 2.1 0.8 5.1 0.9 2.0 0.7 45 24 30 36 24 25 12 17 12 7 10 5 3
mA mA mA mA mA mA mA mA
IDD1
VDD = 5.0 V 10%Note 7 VDD = 3.0 V 10%Note 8 HALT mode Low voltage modeNote 10
Low current consumption mode Note 11
IDD2
VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C Low voltage modeNote 10
Low current consumption mode Note 11 VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 3.0 V, TA = 25C VDD = 3.0 V 10% VDD = 3.0 V, TA = 25C
IDD3
32.768 kHz Note 9 crystal oscillation
A A A A A A A A A A A A A
IDD4
HALT mode
IDD5
XT1 = 0 VNote 12
VDD = 5.0 V 10% VDD = 3.0 V 10% TA = 25C
STOP mode
0.02
Notes 1. 2.
When 1.8 V VDD < 2.7 V, TA = -10 to +85C. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. 3. Either RLCD1 or RLCD2 can be selected by mask option. 4. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. 5. The current flowing through the internal pull-up resistor and the LCD divider resistor is not included. 6. Including the case when the subsystem clock oscillates. 7. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 8. When the device operates in low-speed mode with PCC set to 0000. 9. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 10. When the sub-oscillator control register (SOS) is set to 0000. 11. When SOS is set to 0010. 12. When SOS is set to 00X1, and the feedback resistor of the sub-oscillator is not used (X: don't care).
Data Sheet U11662EJ2V0DS00
63
PD753012A, 753016A, 753017A
AC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter CPU clock cycle time Note 1 tCY Symbol
Operates with main system clock Operates with subsystem clock
Conditions VDD = 2.7 to 5.5 V
MIN. 0.67 0.95 114
TYP.
MAX. 64 64
Unit
s s s
MHz kHz
(minimum instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency fTI
122
125
VDD = 2.7 to 5.5 V
0 0
1 275
TI0, TI1, TI2 input high-, low-level width Interrupt input high-, low-level width
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48 1.8
s s s s s s s
tINTH, tINTL
INT0
IM02 = 0 IM02 = 1
Note 2 10 10 10 10
INT1, 2, 4 KR0-KR7 RESET low-level width tRSL
Notes 1.
The cycle time of the CPU clock () is determined by the oscillation frequency of the connected resonator, the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock.
6 5 Operation guaranteed range
Cycle time tCY [ s]
tCY vs VDD (with main system clock) 64 60
4 3
2.
2tCY or 128/fX depending on the setting of the interrupt mode register (IM0).
2
1
0.5
0
1
2
3
4
5
6
Supply voltage VDD [V]
64
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level width SINote 1 tKL1 tKH1 setup time tSIK1 VDD = 2.7 to 5.5 V (to SCK ) SINote 1 hold time (from SCK ) SCK SONote 1 output delay time tKSO1 RL = 1 k,
Note 2
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150 150 500
tKSI1
VDD = 2.7 to 5.5 V
400 600 VDD = 2.7 to 5.5 V 0 0 250 1000
ns ns
CL = 100 pF
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level width SINote 1 setup time (to SCK ) SINote 1 hold time (from SCK ) SCK SONote 1 output delay time tKSO2 RL = 1 k,
Note 2
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
tKL2 tKH2 tSIK2
VDD = 2.7 to 5.5 V
400 1600
VDD = 2.7 to 5.5 V
100 150
tKSI2
VDD = 2.7 to 5.5 V
400 600 VDD = 2.7 to 5.5 V 0 0 300 1000
ns ns
CL = 100 pF
Notes 1. 2.
Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
Data Sheet U11662EJ2V0DS00
65
PD753012A, 753016A, 753017A
SBI mode (SCK *** internal clock output (master)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level width tKL3 tKH3 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
tKCY3/2-50 tKCY3/2-150
tSIK3
VDD = 2.7 to 5.5 V
150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
SBI mode (SCK *** external clock input (slave)): (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level width tKL4 tKH4 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k, CL = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
400 1600
tSIK4
VDD = 2.7 to 5.5 V
100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000
ns ns ns ns ns ns
Note
RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line.
66
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
AC timing test points (except X1 and XT1 inputs)
VIH (MIN.) VIL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VOH (MIN.) VOL (MAX.)
Clock timing
1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V
1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V
TI0, TI1, TI2 timing
1/fTI tTIL tTIH
TI0, TI1, TI2
Data Sheet U11662EJ2V0DS00
67
PD753012A, 753016A, 753017A
Serial transfer timing 3-wire serial I/O mode
tKCY1,2 tKL1,2 tKH1,2
SCK
tSIK1,2
tKSI1,2
SI
Input data
tKSO1,2
SO
Output data
2-wire serial I/O mode
tKCY1,2 tKL1,2 tKH1,2
SCK
tSIK1,2
tKSI1,2
SB0, 1
tKSO1,2
68
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Serial transfer timing Bus release signal transfer
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4
SB0, 1 tKSO3, 4
Command signal transfer
tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4
SB0, 1 tKSO3, 4
Interrupt input timing
tINTL tINTH
INT0, 1, 2, 4 KR0-7
RESET input timing
tRSL
RESET
Data Sheet U11662EJ2V0DS00
69
PD753012A, 753016A, 753017A
Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85C)
Parameter Data retention power supply voltage Release signal setup time Oscillation stabilization wait time Note 1 Symbol VDDDR tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 1.8 0 Note 2 Note 3 TYP. MAX. 5.5 Unit V
s
ms ms
Notes 1. 2. 3.
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Either 217/fX or 2 15/fX can be selected by mask option. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
Wait Time fX = 4.19 MHz - - - - 0 0 1 1 0 1 0 1 0 1 1 1 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.81 ms) 213/fX (approx. 1.95 ms) fX = 6.0 MHz 220/fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms)
BTM3
BTM2
BTM1
BTM0
Data retention timing (when STOP mode released by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution
VDDDR
tSREL
RESET
tWAIT
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
HALT mode STOP mode Data retention mode Operation mode
VDD STOP instruction execution Standby release signal (interrupt request)
VDDDR
tSREL
tWAIT
70
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
13. CHARACTERISTICS CURVES (REFERENCE VALUES)
IDD vs VDD (fX = 4.19 MHz, fXT = 32.768 kHz)
10 (TA = 25C)
5.0
PCC = 0011
1.0
PCC = 0010 PCC = 0001 PCC = 0000
0.5
Main system clock HALT mode + 32 kHz oscillation
Supply current IDD (mA)
0.1
0.05
Subsystem clock operation mode (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01
0.005 X1 X2 XT1 XT2
Crystal resonator 4.19 MHz Crystal resonator 330 k 32.768 MHz
22 pF
22 pF VSS
22 pF VSS
22 pF
0.001 0 1 1.8 2 3 4 Supply voltage VDD (V) 5 5.5 6 7
Data Sheet U11662EJ2V0DS00
71
PD753012A, 753016A, 753017A
IOH vs VDD-VOH (Ports 2, 3, 6, 7)
(TA = 25C) 15
10
VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V
VDD = 2.2 V
IOH [mA]
5
VDD = 1.8 V
0 0 0.5 1.0 1.5 VDD-VOH [V] 2.0 2.5 3.0
IOL vs VOL (Ports 2, 3, 6, 7)
(TA = 25C) 40
30
VDD = 5 V VDD = 4 V VDD = 5.5 V VDD = 3 V VDD = 2.2 V
IOL [mA]
20
VDD = 1.8 V
10
0 0 0.5 1.0 VOL [V] 1.5 2.0
72
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
14. PACKAGE DRAWINGS
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S CD Q R
80 1
21 20
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. S80GC-65-3B9-6
Data Sheet U11662EJ2V0DS00
73
PD753012A, 753016A, 753017A
80-PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end S C D R Q
80 1
21 20
F J G P H I
M
K S N S L M
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
74
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
80 PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D Q R
80 1 20
21
F G P H I
M
J K M
N
NOTE
S
L
S
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.000.20 12.000.20 12.000.20 14.000.20 1.25 1.25 0.22 +0.05 -0.04 0.10 0.50 (T.P.) 1.000.20 0.500.20 0.145 +0.055 -0.045 0.10 1.050.07 0.100.05 55 1.27 MAX. P80GK-50-BE9-6
Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
Data Sheet U11662EJ2V0DS00
75
PD753012A, 753016A, 753017A
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
A B
60 61
41 40
detail of lead end S C D P T
80 1 F G H I
M
21 20 Q J
R
L U
K S N
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
S
M
ITEM A B C D F G H I J K L M N P Q R S T U
MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.1450.05 0.08 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P80GK-50-9EU-1
76
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
15. RECOMMENDED SOLDERING CONDITIONS
Solder the PD753017A under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions of Surface Mount Type (1/2) (1) PD753012AGC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm)
PD753016AGC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm) PD753017AGC-XXX-3B9: 80-pin plastic QFP (14 x 14 mm, resin thickness 2.7 mm)
Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 3 max. Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 3 max. Solder temperature: 260C or below, Time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-00-3 VP15-00-3 WS60-00-1
Partial heating
-
(2) PD753012AGC-XXX-8BT: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)
PD753016AGC-XXX-8BT: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm) PD753017AGC-XXX-8BT: 80-pin plastic QFP (14 x 14 mm, resin thickness 1.4 mm)
Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max. Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max. Solder temperature: 260C or below, Time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120C or below (package surface temperature) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-00-2 VP15-00-2 WS60-00-1
Partial heating
-
Caution Do not use two or more soldering methods in combination (except the partial heating method).
Data Sheet U11662EJ2V0DS00
77
PD753012A, 753016A, 753017A
Table 15-1. Soldering Conditions of Surface Mount Type (2/2) (3) PD753012AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm)
PD753016AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm) PD753017AGK-XXX-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.05 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours.) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 3 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours.) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-107-3
VPS
VP15-107-3
Partial heating
-
Note
The number of days for storage after the dry pack has been opened. 25C, 65% RH max.
The storage conditions are
(4) PD753012AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm)
PD753016AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm) PD753017AGK-XXX-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12 mm, resin thickness 1.00 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Reflow time: 30 seconds or below (210C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours.) Package peak temperature: 215C, Reflow time: 40 seconds or below (200C or higher), Number of reflow processes: 2 max., Exposure limit: 7 daysNote (After that, prebaking is necessary at 125C for 10 hours.) Pin temperature: 300C or below, Time: 3 seconds or below (per side of device) Symbol IR35-107-2
VPS
VP15-107-2
Partial heating
-
Note
The number of days for storage after the dry pack has been opened. 25C, 65% RH max.
The storage conditions are
Caution Do not use two or more soldering methods in combination (except the partial heating method).
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Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
APPENDIX A. PD75316B, 753017A AND 75P3018A FUNCTION LIST
Parameter Program memory
PD75316B
Mask ROM 0000H-3F7FH (16256 x 8 bits)
PD753017A
Mask ROM 0000H-5FFFH (24576 x 8 bits) 000H-3FFH (1024 x 4 bits)
PD75P3018A
One-time PROM 0000H-7FFFH (32768 x 8 bits)
Data memory
CPU Instruction execution time When main system clock is selected When subsystem clock is selected Pin connection 44 47 48 50-53 57 Stack SBS register
75X Standard 0.95, 1.91, 15.3 s (at 4.19 MHz operation) 122 s (32.768 kHz operation)
75XL CPU * 0.95, 1.91, 3.81, 15.3 s (at 4.19 MHz operation) * 0.67, 1.33, 2.67, 10.7 s (at 6.0 MHz operation)
P12/INT2 P21 P22/PCL P30-P33 IC None
P12/INT2/TI1/TI2 P21/PTO1 P22/PCL/PTO2 P30/MD0-P33/MD3 VPP SBS.3 = 1: Mk I mode selection SBS.3 = 0: Mk II mode selection n00H-nFFH (n = 0-3) Mk I mode: 2-byte stack Mk II mode: 3-byte stack
Stack area Subroutine call instruction stack operation Instruction BRA !addr1 CALLA !addr1 MOVT XA, @BCDE MOVT XA, @BCXA BR BCDE BR BCXA CALL !addr CALLF !faddr Timer
000H-0FFH 2-byte stack
Unavailable
Mk I mode: unavailable Mk II mode: available Available
3 machine cycles 2 machine cycles 3 channels * Basic interval timer: 1 channel * 8-bit timer/event counter: 1 channel * Watch timer: 1 channel
Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles 5 channels * Basic interval timer/watchdog timer: 1 channel * 8-bit timer/event counter: 3 channels (can be used as 16-bit timer/event counter, carrier generator, timer with gate) * Watch timer: 1 channel
Data Sheet U11662EJ2V0DS00
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PD753012A, 753016A, 753017A
Parameter Clock output (PCL)
PD75316B
, 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation)
PD753017A
PD75P3018A
* , 524, 262, 65.5 kHz (Main system clock: at 4.19 MHz operation) * , 750, 375, 93.8 kHz (Main system clock: at 6.0 MHz operation) * 2, 4, 32 kHz (Main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) * 2.93, 5.86, 46.9 kHz (Main system clock: at 6.0 MHz operation)
BUZ output
2 kHz (Main system clock: at 4.19 MHz operation)
Serial interface
3 modes are available * 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit * 2-wire serial I/O mode * SBI mode None Provided
SOS register
Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1)
None
Provided
Register bank selection register (RBS) Standby release by INT0 Interrupt priority selection register (IPS) Vectored interrupt Supply voltage Operating ambient temperature Package
None Unavailable None External: 3, internal: 3 VDD = 2.0 to 6.0 V TA = -40 to +85C
Yes Available Yes External: 3, internal: 5 VDD = 1.8 to 5.5 V
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin plastic QFP (14 x 14 mm)
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Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the PD753017A. The 75XL series uses a common relocatable assembler, in combination with a device file matching each machine. Language processor
RA75X relocatable assembler Part Number (product name)
Host Machine OS PC-9800 series MS-DOSTM Ver. 3.30 to Ver. 6.2Note IBM PC/ATTM and compatible machines Refer to OS for IBM PC 3.5-inch 2HC Supply media 3.5-inch 2HD
S5A13RA75X
S7B13RA75X
Device file
Host Machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Refer to OS for IBM PC 3.5-inch 2HC Supply media 3.5-inch 2HD
Part Number (product name)
S5A13DF753017
S7B13DF753017
Note
Ver. 5.00 or later is provided with a task swap function, but it does not work with this software. The operation of the assembler and device file is guaranteed only on the above host machines and OSs.
Remark
Data Sheet U11662EJ2V0DS00
81
PD753012A, 753016A, 753017A
PROM write tools
Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single-chip microcontroller containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. PROM programmer adapter common to PD75P3018GC-3B9. Connect the programmer adapter to PG-1500 for use. PA-75P316BGK PROM programmer adapter common to PD75P3018GK-BE9. Connect the programmer adapter to PG-1500 for use. PROM programmer adapter common to PD75P3018AGC-8BT. Connect the programmer adapter to PG-1500 for use. PROM programmer adapter common to PD75P3018AGK-9EU. Connect the programmer adapter to PG-1500 for use. PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is controlled on the host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note IBM PC/AT and compatible machines Refer to OS for IBM PC 3.5-inch 2HD Supply media 3.5-inch 2HD Part number (product name)
PA-75P316BGC
PA-75P3018AGC-8BT
PA-75P3018AGK-9EU
Software
PG-1500 controller
S5A13PG1500
S7B13PG1500
Note
Ver.5.00 or later is provided with a task swap function, but it does not work with this software. The operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.
Remark
82
Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
Debugging tool The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
PD753017A.
The system configurations are described as follows.
Hardware IE-75000-RNote 1 In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753017 subseries, the emulation board IE-75300-R-EM and emulation probe that are sold separately must be used with the IE-75000-R. By connecting with the host machine and the PROM programmer, efficient debugging can be made. It contains the emulation board IE-75000-R-EM which is connected. In-circuit emulator for debugging the hardware and software when developing the application systems that use the 75X series and 75XL series. When developing a PD753017 subseries, the emulation board IE-75300-R-EM and emulation probe which are sold separately must be used with the IE-75001-R. It can debug the system efficiently by connecting the host machine and PROM programmer. IE-75300-R-EM Emulation board for evaluating the application systems that use the PD753017 subseries. It must be used with the IE-75000-R or IE-75001-R. Emulation probe for the PD753017AGC. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion socket EV-9200GC-80 which facilitates connection to a target system. Emulation probe for the PD753017AGK. It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM. It is supplied with the 80-pin conversion adapter TGK-080SDW which facilitates connection to a target system. Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix I/F and controls the IE-75000-R or IE-75001-R on a host machine. Host machine OS PC-9800 series MS-DOS Ver. 3.30 to Ver. 6.2Note 3 IBM PC/AT and compatible machines Refer to OS for IBM PC 3.5-inch 2HC 5-inch 2HC Supply media 3.5-inch 2HD 5-inch 2HD Part number (product name)
IE-75001-R
EP-753017GC-R
EV-9200GC-80 EP-753017GK-R
TGK-080SDWNote 2 Software IE control program
S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X
Notes 1. 2.
Maintenance parts This is a product of TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics 2nd Department (TEL +81-6-6244-6672)
3.
Ver.5.00 or later is provided with a task swap function, but it dose not work with this software.
Remarks 1. The operation of the IE control program is guaranteed only on the above host machines and OSs. 2. The PD753012, 753016, 753017, 75P3018, 753012A, 753016A, 753017A, and 75P3018A are commonly referred to as the PD753017 subseries.
Data Sheet U11662EJ2V0DS00
83
PD753012A, 753016A, 753017A
OS for IBM PC The following IBM PC OS's are supported.
OS PC DOSTM Version Ver. 5.02 to Ver. 6.3 J6.1/VNote to J6.3/VNote Ver. 5.0 to Ver. 6.22 5.0/VNote to 6.2/VNote J5.02/VNote
MS-DOS
IBM DOSTM
Note
Only English version is supported.
Caution Ver. 5.0 or later is provided with a task swap function, but it does not work with this software.
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Data Sheet U11662EJ2V0DS00
PD753012A, 753016A, 753017A
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Related Documents
Document No. Japanese English U11662E (this document) U11917E U11282E -- U10453E
Document Name
PD753012A, 753016A, 753017A Data Sheet PD75P3018A Data Sheet PD753017 User's Manual PD753017 Instruction Table
75XL Series Selection Guide
U11662J U11917J U11282J IEM-5598 U10453J
Development Tool Related Documents
Document No. Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-753017GC/GK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) Base IBM PC Series (PC DOS) Base EEU-846 U11354J EEU-967 U11940J U12622J U12385J EEU-704 EEU-5008 English EEU-1416 EEU-1493 EEU-1495 U11940E U12622E U12385E EEU-1291 U10540E
Document Name
Other Related Documents
Document No. Japanese SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcontroller-Related Products by Third Parties C10535J C11531J C10983J C11892J U11416J X13769X C10535E C11531E C10983E C11892E - English
Document Name
Caution The above related documents are subject to change without notice. For design purpose, etc., be sure to use the latest documents.
Data Sheet U11662EJ2V0DS00
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PD753012A, 753016A, 753017A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD753012A, 753016A, 753017A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U11662EJ2V0DS00
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PD753012A, 753016A, 753017A
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is current as of April, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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